1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and, more particularly, to a control voltage generation circuit for controlling an operation of a circuit that senses a variation in current amount of a signal transmission line connected to an internal circuit and detects an operation state of the internal circuit.
2. Description of the Related Art
Recently, demand for a non-volatile semiconductor memory device has increased. Further, to develop a memory device of a large capacity, research has been actively conducted for a high integration of a memory device.
FIG. 1 is a block diagram illustrating a conventional non-volatile memory device.
Referring to FIG. 1, the non-volatile memory device induces a memory cell array 10, which has a plurality of memory cells, and a page buffer 20.
The page buffer 20 includes a bit line selection unit 21, a precharge unit 22, and a register 23. The bit line selection unit 21 is connected between bit lines BLe and BLo and a sensing node SO. The precharge unit 22 is connected to the sensing node SO. The register 23 is connected between the sensing node SO and an input/output terminal YA. The register 23 includes a latch 24, which latches data.
The page buffer 20 transmits data to be stored to the bit line BLe or BLo and latches read data transmitted through the bit line BLe or BLo from the memory cell array 10 in the latch 24 of the register 23 via the sensing node SO precharged by the precharge unit 22. The sensing node SO is precharged by the precharge unit 22 during various operations of the non-volatile memory device.
In a read operation for identifying a state of a cell, cell current of a cell to be read is sensed through the bit line BLe or BLo, and the state of the cell is identified according to a sensing result. For example, in the case where the cell to be read has stored data and the cell current does not flow, the voltage level of the bit line BLe or BLo will retain the level as it is, and, in the case where the cell to be read does not have stored data and the cell current flows, the voltage level of the bit line BLe or BLo will fall lower than a preset level. These states are detected through the sensing node SO, and the state of the cell is identified.
However, as the degree of integration of a non-volatile memory device increases and low power is used, the cell current of a cell gradually decreases. Accordingly in a read operation, a variation range in the voltage level of the bit line BLe or BLo for identifying the state of a cell narrows, and a reading margin gradually decreases by that extent. Therefore, since it takes a long time to identify the state of a cell with the narrowed variation range in the voltage level of the bit line, operation speed of the device is likely to decrease.